(1) Field of the Invention
The present invention relates to a test mode setting circuit for a semiconductor device, and more particularly to a test mode setting circuit for a test circuit in a semiconductor memory in which a change to a test mode is made using a high voltage detection circuit.
(2) Description of the Related Art
The advancement in a fine processing technology for semiconductor elements has made it possible to produce a semiconductor memory device with an increased capacity. In a typical DRAM as an example, the degree of integration has advanced four times in every three recent years. The application of such a device is increasingly expanded in fields such as information, communication, sound and image processing, and the advanced technology is contributing to the enhancement of the device performance and the miniaturization of the device as well as the decrease in power consumption.
However, the increase in the memory capacity has resulted in increasing the time required for conducting tests of the semiconductor memory circuits, and this has become one of the causes for hindering the productivity in the manufacturing of semiconductor devices equipped with memory circuits.
For this reason, the circuit for testing a memory circuit has been proposed in various ways. FIG. 1 is a block diagram of the overall structure of a semiconductor memory equipped with a test mode setting circuit of the kind proposed, and FIG. 2 is a block diagram showing the main portion of the test mode setting circuit. The circuit shown comprises a clock generator 1b, lower row address buffers 2a-21, an uppermost row address buffer 2m, a row decoder 3, a memory cell array 4, a sense amplifier 5, a column address buffer 6, a column decoder 7, a data output buffer 8, a high voltage detection circuit 9, and a data input buffer 10. The clock generator 1b produces predetermined internal clock signals in response to inverted RAS (Row Address Strobe) signals, inverted CAS (Column Address Strobe) signals, inverted WE (Write Enable) signals and inverted OE (Output Enable) signals which are synchronized with clocks. The row address buffers 2a-21 receive, from the outside, signals A0-A11 among the multiplexed address signals A0-A12, and distribute them as internal row address signals .phi.A0-.phi.A11. The row address buffer 2m provides an internal row address signals .phi.A12 from the signal A12, and receives a high voltage of, for example, 10 V, for the test mode setting. The row decoder 3 carries out decoding by using the row address signals .phi.A0-.phi.A12 such that, in the case of, for example, a 64 Mbit DRAM, one of 2.sup.13 of word lines is designated. The memory cell array 4 contains, for example, 64.times.10.sup.6 memory cells designated by the row decoder. The sense amplifier 5 amplifies a minute voltage of data read out from the memory cell array. The column address buffer 6 receives the address signals A0-A10 and distributes them as internal column address signals Y0-Y10. The column decoder 7 carries out decoding by using the column address signals Y0-Y10 such that, in the case of the 64 Mbit DRAM, one each of 2.sup.11 of column lines is designated. The data output buffer 8 outputs to the outside the output data of the sense amplifier 5. The high voltage detection circuit 9 outputs a logical high level voltage when a voltage difference between the high voltage supplied from the outside through the common input terminal for the test mode setting and the power source voltage VCC becomes larger than a predetermined voltage. The data input buffer 10 supplies to the sense amplifier an external data received from the input/output terminals I/O1-I/O4.
The clock generator 1b has a row address control circuit 13 whose output signal is the internal clock signal .phi.XA. The row address (X12) buffer 2m outputs through an in-phase buffer 21 an output of a NAND circuit. This NAND circuit is constituted by P-channel MOS transistors P1 and P2 having their sources connected to the power source potential line VCC and drains connected with each other with a node being formed, and N-channel MOS transistors N1 and N2 connected in series between the node and the ground. A drain electrode of the transistor N1 is an output node, and gate electrodes of the transistors P1 and N2 receive the address signal A12 though the input terminal In12 while gate electrodes of the transistors P2 and N1 receive the signal .phi.XA.
The high voltage detection circuit 9 has its input node connected to a common input terminal to which an input node of the row address buffer 2m is commonly connected, and its output node connected to an input node for the signal .phi.sv of the clock generator 1b.
Now, reference is made to FIGS. 1 and 2, as well as FIG. 3 which is a timing chart for use in explaining the operation of the circuit according to the invention. Under the normal operation state, assuming that the power source voltage VCC is 3.3 V, the pulse whose amplitude is about 2.0 V with the mean amplitude being about 1.5 V is supplied to the input terminals In13-In16 which respectively receive the clock synchronization inversion RAS signal, inversion CAS signal, inversion WE signal and inversion OE signal, to the input terminals In0-In12 which receive the address signals A0-A12, and to the input/output (I/O) terminal for inputting and outputting data.
During the reading operation, each of the clock synchronization inversion RAS signal, inversion CAS signal, and inversion OE signal is made a logical low level, thus causing the clock generator 1b to be in an active state.
By the row address (X0-X12) buffers 2a-2m which receive the address signals A0-A12 and the row decoder 3, the word line of a desired memory cell in the memory cell array is selected, and the data read on the data line through the selected memory cell is amplified by the sense amplifying section 5.
On the other hand, by the column address (Y0-Y10) buffer 6 which distributes column addresses Y0-Y10 and the column decoder 7, a desired sense amplifier in the sense amplifying section 5 is selected, and the output data from the selected sense amplifier is amplified at the data output buffer 8 and outputted to the external input/output terminals I/O1-I/O4.
At this time, the state is under a normal operation, and the output signal .phi.sv of the high voltage detection circuit 9 is remaining as a low level, so that the test mode state is in an inactive state.
The high voltage detection circuit 9 is arranged such that the output signal .phi.sv thereof becomes a high level when the voltage difference between the power source voltage VCC and the voltage supplied to the input terminal In12 becomes higher than a predetermined voltage. Thus, when the mode is changed to a test mode, the input terminal In12 is pulled-up to the high voltage and, by the inversion of the output signal .phi.sv of the high voltage detection circuit 9 to a high level, the clock generator 1b to which the .phi.sv is supplied turns to an active state in the test mode. That is, the input terminal In12 serves as a common terminal to which the address signal A12 or the high voltage is supplied.
The clock generator 1b having turned to the active state is now in the test mode so that, when the internal control signal is inputted, the row decoder 3, the column address buffer 6 and the data output buffer 8 as well as the data input buffer 10 are controlled so as to carry out the operation of, for example, multi-bit simultaneous writing and reading.
Another prior art example of the test mode setting circuit equipped with an input circuit is disclosed in Japanese Patent Application Kokai Publication No. Hei 3-142387. The input circuit is disclosed therein in a block diagram without showing a detailed circuit configuration. However, it is general that such a circuit is constituted by a NAND circuit as explained above. This prior art example is shown by a circuit diagram in FIG. 4. As shown in therein, the test mode setting circuit has an input terminal In21 which is common to an input circuit 31 and a high voltage detection circuit 33. When the high voltage is supplied to the input terminal In21, the output level of the high voltage detection circuit 33 is inverted with the mode changing to a test mode, and an input circuit 31 becomes inactive. The test instruction data received from the input terminal In22 is supplied to a latch circuit 34 through an input circuit 32. This latch circuit 34 takes-in data at the inverted output level of the high voltage detection circuit 33 and, when the inverted output level restores to the original level, the data is latched and supplied to the test circuit 35, allowing the test to be carried out. This arrangement, therefore, prevents the occurrence of such a problem that has occurred in the above explained prior art example wherein, if the high voltage is lowered for any reason during the testing, the mode changes to a non-test mode.
In the first prior art input circuit explained above, when the mode is changed to a test mode, the input terminal In12 which is a common terminal for supplying the address signal A12 and the high voltage is pulled-up to the high voltage and, by inverting the output signal .phi.sv of the high voltage detection circuit 9 to a high level, the clock generator 1 to which the signal .phi.sv is supplied is changed to an active state of the test mode.
Specifically, among the P-channel MOS transistors P1 and P2 and the N-channel MOS transistors N1 and N2 that constitute a 2-input NAND circuit in the row address (X12) buffer 2m, the P-channel MOS transistor P1 and the N-channel MOS transistor N2 at the ground potential side have their gate electrodes connected to the input terminal In12. Therefore, under the test mode, the high voltage supplied to the input terminal In12 is directly applied to the gate electrodes of these P-channel MOS transistor P1 and the N-channel MOS transistor N2 at the ground potential side.
Especially, since the N-channel MOS transistor N2 has its source electrode connected to the ground, the voltage across the gate electrode and the source electrode and across the gate electrode and the drain electrode is in the state in which the same electric field as that of the high voltage is applied.
FIG. 5 is a diagram showing the structure of the prior art transistor described above. In this structure, when the voltage across the source electrode 44 and the gate electrode 42 made of polysilicon formed over the P-Si substrate 41 becomes high, the thin gate oxide film 47 having a thickness of about 10 nm is destroyed so that the transistor N2 having a channel 45 formed between the source electrode 44 under the gate region and the diffusion layer 46 of the drain electrode 43 no longer performs amplifying function.
Also, in the input circuit disclosed in Japanese Patent Application Kokai Publication No. Hei 3-142387, which, although illustrated only in a block diagram as shown in FIG. 4, is understood from the general knowledge as being in a NAND circuit form so that the same problem caused by the destruction resulting in the non-performance of the amplifying function occurs as explained above.